Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted to a substrate and encased in a plastic protective covering. The die includes functional features, such as memory cells, processor circuits, imager devices, and interconnecting circuitry. The die also typically includes bond pads electrically coupled to the functional features. The bond pads are electrically connected to pins or other types of terminals that extend outside the protective covering for connecting the die to busses, circuits, and/or other microelectronic assemblies.
Market pressures continually drive manufacturers to reduce the size of semiconductor die packages and to increase the functional capacity of such packages. One approach for achieving these results is to stack multiple semiconductor dies in a single package. The dies in such a package are typically interconnected by electrically coupling the bond pads of one die in the package with bond pads of other die(s) in the package.
A variety of approaches have been used to electrically interconnect the dies within a multi-die package. One existing approach is to use solder balls connected directly between the bond pads of neighboring dies. Another approach is to fuse “bumps” on the bond pads of neighboring dies. However, the foregoing processes can suffer from several drawbacks. For example, in some cases, the connections between bond pads of neighboring dies may be incomplete and/or may fail under certain conditions. In addition, the temperature typically required to form the bonds between neighboring dies may consume a significant portion of the total thermal budget allotted to the package for processing. Accordingly, the bonding process can limit the life of the package and/or the thermal budget available for other processing steps required to form the package. As a result, there remains a need for improved techniques for interconnecting dies within a semiconductor package.